DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1398

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 26 I/O Ports
26.2
Port A is an input/output port with eight pins as shown in figure 26.1.
26.2.1
Table 26.1 lists the port A registers.
Table 26.1 Register Configuration
26.2.2
PADRL is a 16-bit read-only register that stores port A data. The PA7DR to PA0DR bits
correspond to the PA7/AN7/DA1 to PA0/AN0 pins, respectively. The general input function of
the PA7 to PA0 pins is enabled only when the A/D and D/A converters are halted.
Writing to these bits is ignored, and therefore does not affect the pin state. If these bits are read,
the pin state, not the bit value, is directly returned. Note that, however, this register should not be
read during operation of the A/D or D/A converter. Table 26.2 summarizes PADRL read/write
operation.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 1366 of 1650
REJ09B0313-0300
Register Name
Port A data register L
Note:
R/W:
*
Bit:
Depends on the state of the external pin.
Port A
Register Descriptions
Port A Data Register L (PADRL)
15
R
0
-
14
R
0
-
13
R
0
-
Abbreviation
PADRL
12
Port A
R
0
-
11
R
0
-
10
R
Figure 26.1 Port A
0
-
PA7 (input) / AN7 (input) / DA1 (output)
PA6 (input) / AN6 (input) / DA0 (output)
PA5 (input) / AN5 (input)
PA4 (input) / AN4 (input)
PA3 (input) / AN3 (input)
PA2 (input) / AN2 (input)
PA1 (input) / AN1 (input)
PA0 (input) / AN0 (input)
R/W
R
R
9
0
-
R
8
0
-
Initial Value
H'00xx
PA7
DR
R
7
*
PA6
DR
R
6
*
PA5
DR
R
5
*
Address
H'FFFE3802
PA4
DR
R
4
*
PA3
DR
R
3
*
PA2
DR
R
2
*
8, 16
Access Size
PA1
DR
R
1
*
PA0
DR
R
0
*