DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 86

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 2 CPU
2.3
2.3.1
Instructions are RISC type. This section details their functions.
(1)
Basic instructions have a fixed length of 16 bits, improving program code efficiency.
(2)
The SH-2A additionally features 32-bit fixed-length instructions, improving performance and ease
of use.
(3)
Each basic instruction can be executed in one cycle using the pipeline system.
(4)
Longword is the standard data length for all operations. Memory can be accessed in bytes, words,
or longwords. Byte or word data in memory is sign-extended and handled as longword data.
Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It
is also handled as longword data.
Table 2.2
Note: @(disp, PC) accesses the immediate data.
(5)
Basic operations are executed between registers. For operations that involve memory access, data
is loaded to the registers and executed (load-store architecture). Instructions such as AND that
manipulate bits, however, are executed directly in memory.
Rev. 3.00 Sep. 28, 2009 Page 54 of 1650
REJ09B0313-0300
SH2-A CPU
MOV.W
ADD
.DATA.W
16-Bit Fixed-Length Instructions
32-Bit Fixed-Length Instructions
One Instruction per State
Data Length
Load-Store Architecture
Instruction Features
RISC-Type Instruction Set
@(disp,PC),R1
R1,R0
.........
H'1234
Sign Extension of Word Data
Description
Data is sign-extended to 32
bits, and R1 becomes
H'00001234. It is next
operated upon by an ADD
instruction.
Example of Other CPU
ADD.W
#H'1234,R0

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