DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 336

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 9 Bus State Controller (BSC)
9.5.2
(1)
For access to a normal space, this LSI uses strobe signal output in consideration of the fact that
mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see
section 9.5.8, SRAM Interface with Byte Selection. Figure 9.2 shows the basic timings of normal
space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for
one cycle to indicate the start of a bus cycle.
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 32 bits are always
Rev. 3.00 Sep. 28, 2009 Page 304 of 1650
REJ09B0313-0300
Basic Timing
Normal Space Interface
Figure 9.2 Normal Space Basic Access Timing (Access Wait 0)
Note: * The waveform for DACKn is when active low is specified.
Write
Read
A25 to A0
RD/WR
D31 to D0
RD/WR
D31 to D0
DACKn
CKIO
WEn
CSn
RD
BS
*
T1
T2

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