DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 472

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 10 Direct Memory Access Controller (DMAC)
10.4.5
(1)
When the DMAC is the bus master, the number of bus cycles is controlled by the bus state
controller (BSC) in the same way as when the CPU is the bus master. For details, see section 9,
Bus State Controller (BSC).
(2)
Figures 10.13 to 10.16 show the DREQ input sampling timings in each bus mode.
Rev. 3.00 Sep. 28, 2009 Page 440 of 1650
REJ09B0313-0300
Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
Figure 10.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
Number of Bus Cycles
DREQ Pin Sampling Timing
Number of Bus Cycles and DREQ Pin Sampling Timing
CKIO
Bus cycle
DREQ
(Overrun 0 at
high level)
DACK
(Active-high)
CKIO
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
(Rising)
(Active-high)
CKIO
Bus cycle
DREQ
DACK
1st acceptance
1st acceptance
1st acceptance
Non sensitive period
CPU
CPU
CPU
Non sensitive period
Non sensitive period
CPU
CPU
CPU
2nd acceptance
DMAC
DMAC
Acceptance
start
DMAC
Acceptance start
2nd acceptance
2nd acceptance
Acceptance
start
CPU
CPU
CPU

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