DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1260

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 23 USB 2.0 Host/Function Module (USB)
23.4.10 Pipe Schedule
(1)
When the host controller function is selected and UACT has been set to 1, this module generates a
transaction under the conditions noted in table 23.27.
Table 23.27 Conditions for Generating a Transaction
Notes: 1. Symbols (⎯) in the table indicate that the condition is one that is unrelated to the
Rev. 3.00 Sep. 28, 2009 Page 1228 of 1650
REJ09B0313-0300
Transaction
Setup
Control transfer data stage,
status stage, bulk transfer
Interrupt transfer
Isochronous transfer
Conditions for Generating a Transaction
2. This indicates that a transaction is generated regardless of whether or not there is a
3. This indicates that a transaction is generated regardless of whether or not there is any
generating of tokens. “Valid” indicates that, for interrupt transfers and isochronous
transfers, the condition is generated only in transfer frames that are based on the
interval counter. “Invalid” indicates that the condition is generated regardless of the
interval counter.
receive area. If there was no receive area, however, the received data is destroyed.
data to be sent. If there was no data to be sent, however, a zero-length packet is sent.
DIR
⎯*
IN
OUT
IN
OUT
IN
OUT
1
PID
⎯*
BUF
BUF
BUF
BUF
BUF
BUF
1
Conditions for Generation
IITV0
⎯*
Invalid
Invalid
Valid
Valid
Valid
Valid
1
Buffer State SUREQ
⎯*
Receive
area exists
Send data
exists
Receive
area exists
Send data
exists
*
*
2
3
1
1 setting
⎯*
⎯*
⎯*
⎯*
⎯*
⎯*
1
1
1
1
1
1