DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 884

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 17 I
17.4
The I
mode by setting FS in SAR.
17.4.1
Figure 17.3 shows the I
following a start condition always consists of eight bits.
[Legend]
S:
SLA:
R/W:
A:
DATA: Transfer data
P:
Rev. 3.00 Sep. 28, 2009 Page 852 of 1650
REJ09B0313-0300
SDA
SCL
(a) I
(b) I
S
S
1
1
2
2
2
C bus interface 3 can communicate either in I
C bus format (FS = 0)
C bus format (Start condition retransmission, FS = 0)
S
Indicates the direction of data transfer: from the slave device to the master device when
Start condition. The master device drives SDA from high to low while SCL is high.
Slave address
Acknowledge. The receive device drives SDA to low.
Stop condition. The master device drives SDA from low to high while SCL is high.
R/W is 1, or from the master device to the slave device when R/W is 0.
Operation
I
SLA
SLA
2
C Bus Format
7
2
7
C Bus Interface 3 (IIC3)
SLA
1-7
1
1
R/W
R/W
1
1
2
C bus formats. Figure 17.4 shows the I
R/W
8
A
A
1
1
DATA
DATA
A
9
n1
Figure 17.3 I
n
Figure 17.4 I
m1
A
1
A/A
1-7
1
m
DATA
S
1
2
C Bus Formats
2
C Bus Timing
2
C bus mode or clocked synchronous serial
8
SLA
7
A/A
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
1
A
9
1
2
R/W
P
C bus timing. The first frame
1
1
A
1
1-7
DATA
n: Transfer bit count (n = 1 to 8)
m: Transfer frame count (m ≥ 1)
DATA
n2
m2
8
A
9
A/A
1
P
1
P

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