DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 964

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 19 Controller Area Network (RCAN-TL1)
Please note that the CCR value is only embedded on the frame transmitted but not stored back into
Mailbox 30.
When CMAX!= 3'b111, MBC[31] = 3'b011 and TXPR[31] is cleared, Mailbox-31 is configured
as reception of time reference. When a valid reference message is received (DLC > 0) RCAN-TL1
performs internal synchronisation (modifying its RFMK and basic cycle CCR).
(4)
Storage for the Timestamp recorded on messages for transmit/receive. The Timestamp will be a
useful function to monitor if messages are received/transmitted within expected schedule.
• Timestamp
Initial value:
Message Receive: For received messages of Mailbox-15 to 0, Timestamp always captures the
CYCTR (Cycle Time Register) value or Cycle_Counter CCR[5:0] + CYCTR[15:6] value,
depending on the programmed value in the bit 14 of TTCR0 (Timer Trigger Control Register 0) at
SOF.
For messages received into Mailboxes 30 and 31, Timestamp captures the TCNTR (Timer
Counter Register) value at SOF.
Message Transmit: For transmitted messages of Mailbox-15 to 1, Timestamp always captures the
CYCTR (Cycle Time Register) value or Cycle_Counter CCR[5:0] + CYCTR[15:6] value,
depending on the programmed value in the bit 14 of TTCR0 (Timer Trigger Control Register 0), at
SOF.
For messages transmitted from Mailboxes 30 and 31, Timestamp captures the TCNTR (Timer
Counter Register) value at SOF.
Rev. 3.00 Sep. 28, 2009 Page 932 of 1650
REJ09B0313-0300
R/W:
Timestamp
Bit:
H'10A + N*32
H'10C + N*32
H'10E + N*32
H'108 + N*32
MB30 - 31
TS15 TS14 TS13 TS12 TS11
15
R
0
15
14
R
0
Next_is_Gap/Cycle_Counter (first Rx/Tx Byte)
14
13
R
0
13
MSG_DATA_2
MSG_DATA_4
MSG_DATA_6
12
12
R
0
11
Figure 19.5 Message Data Field
11
R
0
10
TS10
9
10
R
0
8
TS9
R
9
0
7
6
TS8
R
8
0
5
MSG_DATA_1
MSG_DATA_3
MSG_DATA_5
MSG_DATA_7
TS7
R
4
7
0
3
TS6
R
6
0
2
TS5
1
R
5
0
0
TS4
R
4
0
Byte/Word/LW
Byte/Word/LW
Byte/Word
Byte/Word
TS3
R
3
0
TS2
R
2
0
Data
TS1
R
1
0
TS0
R
0
0