DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 840

Manufacturer Part Number

DS72030W200FPV

MPU, 32BIT, SH7203, ROMLESS, 240QFP

Manufacturer

Renesas Electronics America

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

1.1V To 1.3V

Operating Temperature Range

-20Â°C To +85Â°C

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Section 16 Synchronous Serial Communication Unit (SSU)

A transfer clock can be selected from among seven internal clocks and an external clock. Before

using this module, enable the SSCK pin function in the PFC. When the MSS bit in SSCRH is 1, an

internal clock is selected and the SSCK pin is used as an output pin. When transfer is started, the

clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the SSCK pin.

When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin.

The relationship of clock phase, polarity, and transfer data depends on the combination of the

CPOS and CPHS bits in SSMR when the value of the SSUMS bit in SSCRL is 0. Figure 16.2

shows the relationship. When SSUMS = 1, the CPHS setting is invalid although the CPOS setting

is valid. When SSUMS = 1, the transmit data change timing and receive data fetch timing are the

same as that shown as “(1) When CPHS = 0” in figure 16.2.

Setting the MLS bit in SSMR selects either MSB first or LSB first communication. When MLS =

0, data is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB

Rev. 3.00 Sep. 28, 2009 Page 808 of 1650

REJ09B0313-0300

(1) When CPHS = 0

(2) When CPHS = 1

Transfer Clock

Relationship of Clock Phase, Polarity, and Data

Figure 16.2 Relationship of Clock Phase, Polarity, and Data