DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 436

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 10 Direct Memory Access Controller (DMAC)
Rev. 3.00 Sep. 28, 2009 Page 404 of 1650
REJ09B0313-0300
Bit
29
28
27 to 24 ⎯
23
22
21
Bit Name
RLDSAR
RLDDAR
DO
TL
⎯
Initial
Value
0
0
All 0
0
0
0
R/W
R/W
R/W
R
R/W
R/W
R
Description
SAR Reload Function ON/OFF
Enables (ON) or disables (OFF) the function to reload
SAR and DMATCR.
0: Disables (OFF) the function to reload SAR and
1: Enables (ON) the function to reload SAR and
DAR Reload Function ON/OFF
Enables (ON) or disables (OFF) the function to reload
DAR and DMATCR.
0: Disables (OFF) the function to reload DAR and
1: Enables (ON) the function to reload DAR and
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid only in level detection by
CHCR_0 to CHCR_3. This bit is reserved in CHCR_4
to CHCR_7; it is always read as 0 and the write value
should always be 0.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
Transfer End Level
Specifies the TEND signal output is high active or low
active. This bit is valid only in CHCR_0 and CHCR_1.
This bit is reserved in CHCR_2 to CHCR_7; it is
always read as 0 and the write value should always be
0.
0: Low-active output from TEND
1: High-active output from TEND
Reserved
This bit is always read as 0. The write value should
always be 0.
DMATCR
DMATCR
DMATCR
DMATCR