DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 163

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 5 Exception Handling
(3)
Power-On Reset Initiated by WDT
When a setting is made for a power-on reset to be generated in the WDT’s watchdog timer mode,
and WTCNT of the WDT overflows, this LSI enters the power-on reset state.
In this case, WRCSR of the WDT and FRQCR of the CPG are not initialized by the reset signal
generated by the WDT.
If a reset caused by the RES pin or the H-UDI reset assert command occurs simultaneously with a
reset caused by WDT overflow, the reset caused by the RES pin or the H-UDI reset assert
command has priority, and the WOVF bit in WRCSR is cleared to 0. When power-on reset
exception processing is started by the WDT, the CPU operates in the same way as when a power-
on reset was caused by the RES pin.
Rev. 3.00 Sep. 28, 2009 Page 131 of 1650
REJ09B0313-0300

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