DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 563

Manufacturer Part Number

DS72030W200FPV

MPU, 32BIT, SH7203, ROMLESS, 240QFP

Manufacturer

Renesas Electronics America

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

1.1V To 1.3V

Operating Temperature Range

-20Â°C To +85Â°C

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer

registers. In channel 0, TGRF can also be used as a buffer register.

Buffer operation differs depending on whether TGR has been designated as an input capture

Note: TGRE_0 cannot be designated as an input capture register and can only operate as a

Table 11.41 shows the register combinations used in buffer operation.

Table 11.41 Register Combinations in Buffer Operation

• When TGR is an output compare register

When a compare match occurs, the value in the buffer register for the corresponding channel is

transferred to the timer general register.

This operation is illustrated in figure 11.14.

compare match register.

Buffer Operation

Figure 11.14 Compare Match Buffer Operation

Timer General Register

Compare match signal

Timer general

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 3.00 Sep. 28, 2009 Page 531 of 1650

Buffer Register

REJ09B0313-0300