DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 592

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(b)
In complementary PWM mode, nine registers are used, comprising compare registers, buffer
registers, and temporary registers. Figure 11.40 shows an example of complementary PWM mode
operation.
The registers which are constantly compared with the counters to perform PWM output are
TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits
OLSN and OLSP in the timer output control register (TOCR) is output.
The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4.
Between a buffer register and compare register there is a temporary register. The temporary
registers cannot be accessed by the CPU.
Data in a compare register is changed by writing the new data to the corresponding buffer register.
The buffer registers can be read or written at any time.
The data written to a buffer register is constantly transferred to the temporary register in the Ta
interval. Data is not transferred to the temporary register in the Tb interval. Data written to a
buffer register in this interval is transferred to the temporary register at the end of the Tb interval.
The value transferred to a temporary register is transferred to the compare register when TCNTS
for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting
down. The timing for transfer from the temporary register to the compare register can be selected
with bits MD3 to MD0 in the timer mode register (TMDR). Figure 11.40 shows an example in
which the mode is selected in which the change is made in the trough.
In the tb interval (tb1 in figure 11.40) in which data transfer to the temporary register is not
performed, the temporary register has the same function as the compare register, and is compared
Rev. 3.00 Sep. 28, 2009 Page 560 of 1650
REJ09B0313-0300
Counter value
TGRA_3
H'0000
TCDR
TDDR
Register Operation
Figure 11.39 Complementary PWM Mode Counter Operation
TCNT_4
TCNTS
TCNT_3
TCNT_3
TCNT_4
TCNTS
Time

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