DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1155

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.3.9
CFIFOSIE is a register that controls the SIE functions of the CFIFO port. This register switches
the access right between the SIE and CPU, clears the SIE buffer memory, and checks whether the
SIE buffer is busy or not. This register is not operational when DCP is selected.
This register is initialized by a power-on reset and a software reset.
Initial value:
Bit
15
14
R/W:
Bit:
R/W* R/W*
TGL
FIFO Port SIE Register (CFIFOSIE)
Bit Name
TGL
SCLR
15
0
SCLR SBUSY
14
0
13
R
0
Initial
Value
0
0
12
R
0
-
11
R
0
-
R/W
R/W*
R/W
10
R
0
-
R
9
0
-
Description
Access Right Switch
Sets the buffer memory on the SIE side to the CPU
side. Set the PID bits to NAK and check that the SIE
does not access the buffer memory with the SBUSY
bit (that the SBUSY bit is cleared to 0). Then write
the TGL bit (toggle operation). This bit is valid only
for pipes for which the receiving direction (reading
from the buffer memory) has been set.
0: Invalid
1: Switches the access right
SIE Buffer Clear
Clears the buffer memory on the SIE side. Set the
PID bits to NAK and check that the SIE does not
access the buffer (SBUSY = 0). Then clear the
buffer. This bit is valid only for pipes for which the
transmitting direction (writing to the buffer memory)
has been set.
0: Invalid
1: Clears buffer memory on SIE side
R
8
0
-
Section 23 USB 2.0 Host/Function Module (USB)
R
7
0
-
Rev. 3.00 Sep. 28, 2009 Page 1123 of 1650
R
6
0
-
R
5
0
-
R
4
0
-
R
3
0
-
REJ09B0313-0300
R
2
0
-
R
1
0
-
R
0
0
-