DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 260

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 8 Cache
8.3
Operations for the operand cache are described here. Operations for the instruction cache are
similar to those for the operand cache except for the address array not having the U bit, and there
being no prefetch operation or write operation, or a write-back buffer.
8.3.1
If the operand cache is enabled (OCE bit in CCR1 is 1), whenever data in a cache-enabled area is
accessed, the cache will be searched to see if the desired data is in the cache. Figure 8.2 illustrates
the method by which the cache is searched.
Entries are selected using bits 10 to 4 of the address used to access memory and the tag address of
that entry is read. At this time, the upper three bits of the tag address are always cleared to 0. Bits
31 to 11 of the address used to access memory are compared with the read tag address. The
address comparison uses all four ways. When the comparison shows a match and the selected
entry is valid (V = 1), a cache hit occurs. When the comparison does not show a match or the
selected entry is not valid (V = 0), a cache miss occurs. Figure 8.2 shows a hit on way 1.
Rev. 3.00 Sep. 28, 2009 Page 228 of 1650
REJ09B0313-0300
Operation
Searching Cache