DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1138

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 23 USB 2.0 Host/Function Module (USB)
Note:
Table 23.3 USB Data Bus Line Status
[Legend]
Chirp:
Squelch:
Not squelch: High-speed J state or high-speed K state
Chirp J:
Chirp K:
Rev. 3.00 Sep. 28, 2009 Page 1106 of 1650
REJ09B0313-0300
Bit
1, 0
LNST[1]
0
0
1
1
* Depending on the D+ and D− line status.
Bit Name
LNST[1:0]
The reset handshake protocol is being executed in high-speed operation enabled
state (the HSE bit in SYSCFG is set to 1).
SE0 or idle state
Chirp J state
Chirp K state
LNST[0]
0
1
0
1
Initial
Value
*
During Full-Speed
Operation
SE0
J state
K state
SE1
R/W
R
Description
USB Data Line Status
Table 23.3 shows the USB data bus line status. The
line status (D+ and D− lines) of the USB data bus is
monitored using the setting of these bits.
The line status can be confirmed with the full-speed
receiver. This module automatically controls the full-
speed receiver by supplying USBCLK. However, the
full-speed receiver can be enabled using software,
without supplying USBCLK, by setting the FSRPC bit
in SYSCFG. After a power-on reset, D+ and D− line
status can be confirmed prior to the USBCLK supply
by setting the FSRPC bit to 1.
Once USBCLK is supplied, software setting is not
required.
During High-Speed
Operation
Squelch
Not squelch
Invalid
Invalid
During Chirp
Operation
Squelch
Chirp J
Chirp K
Invalid