DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1008

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 19 Controller Area Network (RCAN-TL1)
Bit 11 — TCMR1 compare match enable: When this bit is set, IRR15 is set by TCMR1
compare match.
Bit 10 — TCMR0 compare match enable: When this bit is set, IRR14 is set by TCMR0
compare match.
Bits 9 to 7: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bit 6 — Timer Clear-Set Control by TCMR0: Specifies if the Timer is to be cleared and set to
H'0000 when the TCMR0 matches to the TCNTR. Please note that the TCMR0 is also capable to
generate an interrupt signal to the CPU via IRR14.
Note: If RCAN-TL1 is working in TTCAN mode (CMAX isn't 3'b111), TTCR0 bit6 has to be
Rev. 3.00 Sep. 28, 2009 Page 976 of 1650
REJ09B0313-0300
Bit11 TTCR0 11
0
1
Bit10 TTCR0 10
0
1
Bit6: TTCR0 6
0
1
‘0’ to avoid clearing Local Time.
Description
IRR15 isn't set by TCMR1 compare match (initial value)
IRR15 is set by TCMR1 compare match
Description
IRR14 isn't set by TCMR0 compare match (initial value)
IRR14 is set by TCMR0 compare match
Description
Timer is not cleared by the TCMR0 (initial value)
Timer is cleared by the TCMR0

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