DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1301

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.4
24.4.1
This LCDC is capable of controlling displays with up to 1024 × 1024 dots and 16 bpp (bits per
pixel). The image data for display is stored in VRAM, which is shared with the CPU. This LCDC
should read the data from VRAM before display.
This LSI has a maximum 32-burst memory read operation and a 2.4-kbyte line buffer, so although
a complete breakdown of the display is unlikely, there may be some problems with the display
depending on the combination.
As a rough standard, the bus occupation ratio shown below should not exceed 40%.
The overhead coefficient becomes 1.375 when the CL2 SDRAM is connected to a 32-bit data bus
and 1.188 when connected to a 16-bit data bus.
Bus occupation ratio (%) =
Operation
LCD Module Sizes which Can Be Displayed in this LCDC
Overhead coefficient x Total number of display pixels ((HDCN + 1) x 8 x (VDLN + 1))
x Frame rate (Hz) x Number of colors (bpp)
CKIO (Hz) x Bus width (bit)
Rev. 3.00 Sep. 28, 2009 Page 1269 of 1650
Section 24 LCD Controller (LCDC)
REJ09B0313-0300
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