DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 815

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In serial reception, the SCIF operates as described below.
1. The SCIF synchronizes with serial clock input or output and starts the reception.
2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the
3. After setting RDF to 1, if the receive FIFO data full interrupt enable bit (RIE) is set to 1 in
Figure 15.17 shows an example of SCIF receive operation.
Serial clock
Serial data
data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this
check is passed, the RDF flag is set to 1 and the SCIF stores the received data in SCFRDR. If
the check is not passed (overrun error is detected), further reception is prevented.
SCSCR, the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and
the receive-data-full interrupt enable bit (RIE) or the receive error interrupt enable bit (REIE)
in SCSCR is also set to 1, the SCIF requests a break interrupt (BRI).
ORER
RDF
RXI
interrupt
request
Figure 15.17 Example of SCIF Receive Operation
Bit 7
Data read from SCFRDR and
RDF flag cleared to 0 by RXI
interrupt handler
Bit 0
LSB
One frame
Section 15 Serial Communication Interface with FIFO (SCIF)
Bit 7
MSB
Bit 0
RXI
interrupt
request
Rev. 3.00 Sep. 28, 2009 Page 783 of 1650
Bit 1
BRI interrupt request
by overrun error
Bit 6
REJ09B0313-0300
Bit 7