DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 386

Manufacturer Part Number

DS72030W200FPV

MPU, 32BIT, SH7203, ROMLESS, 240QFP

Manufacturer

Renesas Electronics America

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

1.1V To 1.3V

Operating Temperature Range

-20Â°C To +85Â°C

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)

(12) Power-On Sequence

In order to use SDRAM, mode setting must first be made for SDRAM after waiting for the

designated pause interval after powering on. This pause interval should be provided by a power-on

reset generating circuit or software.

To perform SDRAM initialization correctly, the bus state controller registers must first be set,

followed by a write to the SDRAM mode register. In SDRAM mode register setting, the address

signal value at that time is latched by a combination of the CSn, RASU, RASL, CASU, CASL,

and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be

written to the SDRAM mode register by performing a write to address H'FFFC4000 + X for area 2

SDRAM, and to address H'FFFC5000 + X for area 3 SDRAM. In this operation the data is

ignored, but the mode write is performed as a byte-size access. To set burst read/single write, CAS

latency 2 to 3, wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is

written in a byte-size access to the addresses shown in table 9.18. In this time 0 is output at the

external address pins of A12 or later.

Table 9.18 Access Address in SDRAM Mode Register Write

• Setting for Area 2

Rev. 3.00 Sep. 28, 2009 Page 354 of 1650

REJ09B0313-0300

Data Bus Width

Data Bus Width

Burst read/single write (burst length 1):

Burst read/burst write (burst length 1):

Access Address

Access Address

External Address Pin

External Address Pin