DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 997

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

• TXCR0
Note: * Only writing a ‘1’ to a Mailbox that is requested for transmission and is configured as
Bits 15 to 1 — Requests the corresponding Mailbox, that is in the queue for transmission, to
cancel its transmission. The bit 15 to 1 corresponds to Mailbox-15 to 1 (and TXPR0[15:1])
respectively.
Bit 0 — This bit is always ‘0’ as this is a receive-only mailbox. Writing a ‘1’ to this bit position
has no effect and always read back as a ‘0’.
(3)
The TXACK1 and TXACK0 are 16-bit read/conditionally-write registers. These registers are used
to signal to the CPU that a mailbox transmission has been successfully made. When a transmission
has succeeded the RCAN-TL1 sets the corresponding bit in the TXACK register. The CPU may
clear a TXACK bit by writing a ‘1’ to the corresponding bit location. Writing a ‘0’ has no effect.
• TXACK1
Note: * Only when writing a ‘1’ to clear.
Bit[15:1]: TXCR0
0
1
Initial value:
Initial value:
Transmit Acknowledge Register (TXACK1, TXACK0)
R/W:
R/W:
Bit:
Bit:
transmit.
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
15
15
0
0
14
14
0
0
Description
Transmit message cancellation idle state in corresponding mailbox (Initial
value)
[Clearing Condition]
Completion of transmit message cancellation (automatically cleared)
Transmission cancellation request made for corresponding mailbox
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
9
0
9
0
TXCR0[15:1]
TXACK1[15:0]
8
0
8
0
Section 19 Controller Area Network (RCAN-TL1)
7
0
7
0
Rev. 3.00 Sep. 28, 2009 Page 965 of 1650
6
0
6
0
5
0
5
0
4
0
4
0
3
0
3
0
REJ09B0313-0300
2
0
2
0
1
0
1
0
R
0
0
0
0
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