DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 531

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3.13 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0
to 4.
When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT
counter.
Bit
7
6
5 to 3
2
1
0
Bit Name
CST4
CST3
—
CST2
CST1
CST0
Initial value:
Initial
Value
0
0
All 0
0
0
0
R/W:
Bit:
CST4
R/W
7
0
R/W
R/W
R/W
R
R/W
R/W
R/W
CST3
R/W
6
0
Description
Counter Start 4 and 3
These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but
the TIOC pin output compare output level is retained. If
TIOR is written to when the CST bit is cleared to 0, the
pin output level will be changed to the set initial output
value.
0: TCNT_4 and TCNT_3 count operation is stopped
1: TCNT_4 and TCNT_3 performs count operation
Reserved
These bits are always read as 0. The write value should
always be 0.
Counter Start 2 to 0
These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but
the TIOC pin output compare output level is retained. If
TIOR is written to when the CST bit is cleared to 0, the
pin output level will be changed to the set initial output
value.
0: TCNT_2 to TCNT_0 count operation is stopped
1: TCNT_2 to TCNT_0 performs count operation
R
5
0
-
R
4
0
-
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
R
3
0
-
Rev. 3.00 Sep. 28, 2009 Page 499 of 1650
CST2
R/W
2
0
CST1
R/W
1
0
CST0
R/W
0
0
REJ09B0313-0300