DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 90

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 2 CPU
2.3.2
Addressing modes and effective address calculation are as follows:
Table 2.8
Rev. 3.00 Sep. 28, 2009 Page 58 of 1650
REJ09B0313-0300
Addressing
Mode
Register direct
Register indirect @Rn
Register indirect
with post-
increment
Register indirect
with pre-
decrement
Addressing Modes
Addressing Modes and Effective Addresses
Instruction
Format
Rn
@Rn+
@-Rn
Effective Address Calculation
The effective address is register Rn. (The operand
is the contents of register Rn.)
The effective address is the contents of register Rn.
The effective address is the contents of register Rn.
A constant is added to the contents of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
1/2/4
1/2/4
Rn
Rn
Rn
Rn + 1/2/4
Rn – 1/2/4
+
–
Rn – 1/2/4
Rn
Rn
Equation
—
Rn
Rn
(After
instruction
execution)
Byte:
Rn + 1 → Rn
Word:
Rn + 2 → Rn
Longword:
Rn + 4 → Rn
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction is
executed with
Rn after this
calculation)