DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1227

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

• Bits in PIPEnCTR
(6)
This module automatically toggles the sequence bit in the data PID when data is transferred
normally in the control transfer data stage, bulk transfer and interrupt transfer. The sequence bit of
the data PID that was transmitted can be confirmed with the SQMON bit in DCPCTR and
PIPEnCTR. When data is transmitted, the sequence bit switches at the timing at which the ACK
handshake is received. When data is received, the sequence bit switches at the timing at which the
ACK handshake is transmitted. The SQCLR bit in DCPCTR and the SQSET bit in PIPEnCTR can
be used to change the data PID sequence bit.
When the function controller function has been selected and control transfer is used, this module
automatically sets the sequence bit when a stage transition is made. DATA0 is returned when the
setup stage is ended and DATA1 is returned in a status stage. Therefore, software settings are not
required. However, when the host controller function has been selected and control transfer is
used, the sequence bit should be set by software at the stage transition.
For the Clearfeature request transmission or reception, the data PID sequence bit should be set by
software, regardless of whether the host controller function or function controller function is
selected.
With pipes for which isochronous transfer has been set, sequence bit operation cannot be carried
out using the SQSET bit.
(7)
This module has a function that disables pipe operation (PID response = NAK) at the timing at
which the final data packet of a transaction is received (this module automatically distinguishes
this based on reception of a short packet or the transaction counter) by setting the SHTNAK bit in
PIPECFG to 1.
When a double buffer is being used for the buffer memory, using this function enables reception
of data packets in transfer units. If pipe operation has disabled, the pipe has to be set to the enabled
state again (PID response = BUF) using software.
This function can be used only when bulk transfers are used.
Data PID Sequence Bit
Response PID = NAK Function
Section 23 USB 2.0 Host/Function Module (USB)
Rev. 3.00 Sep. 28, 2009 Page 1195 of 1650
REJ09B0313-0300