DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 146

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 4 Clock Pulse Generator (CPG)
Rev. 3.00 Sep. 28, 2009 Page 114 of 1650
REJ09B0313-0300
Bit
14
13, 12
11, 10
9, 8
Bit Name
CKOEN2
CKOEN[1:0] 00
⎯
STC[1:0]
Initial
Value
0
All 0
00
R/W
R/W
R/W
R
R/W
Description
Clock Output Enable 2
Specifies whether the CKIO pin outputs clock signals
or the CKIO pin is fixed low when the frequency-
multiplier of the PLL circuit is changed.
If this bit is set to 1, the CKIO pin is fixed low while the
frequency-multiplier of the PLL circuit is changed.
Therefore, the malfunction of an external circuit
caused by an unstable CKIO clock when the
frequency-multiplier of the PLL circuit is changed can
be prevented. In clock operating mode 2, the CKIO
pin functions as an input regardless of the value of
this bit.
0: Outputs clock
1: Outputs low level
Clock Output Enable
Specifies the CKIO pin outputs clock signals, or is set
to a fixed level or high impedance (Hi-Z) during
normal operation mode, release of bus mastership,
standby mode, or cancellation of standby mode.
If these bits are set to 01, the CKIO pin is fixed at low
during standby mode or cancellation of standby
mode. Therefore, the malfunction of an external circuit
caused by an unstable CKIO clock during cancellation
of standby mode can be prevented. In clock operating
mode 2, the CKIO pin functions as an input
regardless of the value of these bits. In deep standby
mode, the normal state is retained.
The settings are shown under the CKOEN[1:0] bits in
table 4.5.
Reserved
These bits are always read as 0. The write value
should always be 0.
Frequency Multiplication Ratio of PLL Circuit
00: × 8 time
01: × 12 times
10: × 16 times
11: Reserved (setting prohibited)