DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 701

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
12.3
12.3.1
When an internal clock is selected with the CKS[1:0] bits in CMCSR and the STR bit in CMSTR
is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and
CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the
CMIE bit in CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested.
CMCNT then starts counting up again from H'0000.
Figure 12.2 shows the operation of the compare match counter.
12.3.2
One of four clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the peripheral clock
(Pφ) can be selected with the CKS1 and CKS0 bits in CMCSR. Figure 12.3 shows the timing.
Peripheral clock
Internal clock
Count clock
CMCNT
Operation
Interval Count Operation
CMCNT Count Timing
(Pφ)
CMCOR
H'0000
CMCNT value
Clock
N
Figure 12.2 Counter Operation
Figure 12.3 Count Timing
N
Counter cleared by compare
match with CMCOR
Rev. 3.00 Sep. 28, 2009 Page 669 of 1650
Section 12 Compare Match Timer (CMT)
Clock
N + 1
Time
REJ09B0313-0300
N + 1

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