DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 1010
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 1010 of 1154
- Download datasheet (32Mb)
1–52
Table 1–16. MegaWizard Plug-In Manager Options (PCIe 1) (Part 2 of 2)
Stratix IV Device Handbook Volume 3
Create an rx_patterndetect
output port to indicate pattern
detected.
Create an rx_ctrldetect port to
indicate 8B/10B decoder has
detected a control code.
Create a tx_detectrxloop input
port as Receiver detect or loopback
enable, depending on the power
state.
Create a tx_forceelecidle input
port to force the Transmitter to send
Electrical Idle signals.
Create a
tx_forcedispcompliance input
port to force negative running
disparity.
Create a tx_invpolarity port to
allow Transmitter polarity inversion.
Note to
(1) Refer to the table 'Power States and Functions Allowed in Each Power State' in the PIPE Interface section in the
Stratix IV Devices
Table
ALTGX Setting
1–16:
chapter.
This is an output status signal that the word aligner
forwards to the FPGA fabric to indicate that the word
alignment pattern programmed has been detected in
the current word boundary. The signal width is 1 and
2 bits for a channel width of 8 bits and 16 bits,
respectively.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric. This signal
indicates whether the decoded 8-bit code group is a
data or control code group on this port.
If the received 10-bit code group is one of the 12
control code groups (/Kx.y/) specified in the
IEEE802.3 specification, this signal is driven high. If
the received 10-bit code group is a data code group
(/Dx.y/), this signal is driven low. The signal width is
1 and 2 bits for a channel width of 8 bits and 16 bits,
respectively.
Depending on the power-down mode, asserting this
signal enables either the receiver detect operation or
Loopback mode.
Enabling this port sets the transmitter buffer in
electrical idle mode. This port is available in all PCIe
power-down modes and has a specific use in each
mode.
A high level on this port forces the associated
parallel transmitter data on the tx_datain port to
be transmitted with negative current running
disparity.
■
■
This optional port allows you to dynamically reverse
the polarity of every bit of the data word fed to the
serializer in the transmitter data path. Use this option
when the positive and negative signals of the
differential output from the transmitter
(tx_dataout) are erroneously swapped on the
board.
For 8-bit transceiver channel width
configurations, you must drive
tx_forcedispcompliance[1:0] high in the
same parallel clock cycle as the first /K28.5/ of
the compliance pattern on the tx_datain port.
For 16-bit transceiver channel width
configurations, you must drive only the LSB of
tx_forcedispcompliance[1:0]high in the
same parallel clock cycle as /K28.5/D21.5/ of the
compliance pattern on the tx_datain port.
(1)
(1)
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
“Automatic Synchronization
State Machine Mode Word
Aligner with 10-bit PMA-PCS
Interface Mode” section in the
Transceiver Architecture in
Stratix IV Devices
“8B/10B Decoder” section in
the
in Stratix IV Devices
“Receiver Detection” and
“PCIe Reverse Parallel
Loopback” section in the
Transceiver Architecture in
Stratix IV Devices
“Transmitter Buffer Electrical
Idle” section in the
Transceiver Architecture in
Stratix IV Devices
“Compliance Pattern
Transmission Support”
section in the
Architecture in Stratix IV
Devices
“Transmitter Polarity
Inversion” section in the
Transceiver Architecture in
Stratix IV Devices
February 2011 Altera Corporation
Transceiver Architecture
Transceiver Architecture in
chapter.
Reference
Transceiver
Protocol Settings
chapter.
chapter.
chapter.
chapter.
chapter.
Related parts for DK-DEV-4SGX230N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-DEV-2AGX125N](/photos/28/41/284154/dk-dev-2agx125n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
![DK-DEV-3CLS200N](/photos/9/24/92409/dk-dev-3cls200n_tmb.jpg)
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SE530N](/photos/28/41/284157/dk-dev-4se530n_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
![DK-DEV-2AGX260N](/photos/28/41/284175/dk-dev-2agx260n_tmb.jpg)
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
![DK-DEV-5M570ZN](/photos/18/31/183180/dk-dev-5m570zn_tmb.jpg)
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
![DK-DEV-5SGXEA7/ES](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
![DK-DEV-3SL150N](/photos/9/20/92079/dk-dev-3sl150n_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
![DK-DEV-1AGX60N](/photos/9/31/93181/mfgdk-dev-1agx60n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
![DK-DEV-4CGX150N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SGX530N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: