DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 546

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–102
Figure 1–89. CMU0 PLL
Note to
(1) The inter transceiver block (ITB) clock lines are the maximum value. The actual number of ITB lines in your device depends on the number of
Stratix IV Device Handbook Volume 2: Transceivers
transceiver blocks on one side of your device.
ITB Clock Lines (1)
PLL Cascade Clock
Figure
Global Clock Line
Dedicated refclk0
Dedicated refclk1
1–89:
f
f
1
6
Figure 1–89
You can select the input reference clock to the CMU0 PLL from multiple clock sources:
■
■
■
■
■
The CMU0 PLL generates the high-speed clock from the input reference clock. The PFD
tracks the VCO output with the input reference clock.
For more information about transceiver input reference clocks, refer to the
Clocking in Stratix IV Devices
The VCO in the CMU0 PLL is half rate and runs at half the serial data rate. To generate
the high-speed clock required to support a native data rate range of 600 Mbps to
8.5 Gbps, the CMU0 PLL uses two multiplier blocks (/M and /L) in the feedback path
(shown in
The ALTGX MegaWizard Plug-In Manager provides the list of input reference clock
frequencies based on the data rate you select. The Quartus II software automatically
selects the /M and /L settings based on the input reference clock frequency and serial
data rate.
The CMU0 and CMU1 PLLs have a dedicated pll_locked signal that is asserted to
indicate that the CMU PLL is locked to the input reference clock. You can use the
pll_locked signal in your transceiver reset sequence, as described in the
and Power Down in Stratix IV Devices
PLL cascade clock—the output from the general purpose PLLs in the FPGA fabric
Global clock line—the input reference clock from the dedicated CLK pins are
connected to the global clock line
refclk0—dedicated REFCLK in the transceiver block
refclk1—dedicated REFCLK in the transceiver block
Inter transceiver block lines—the ITB lines connect refclk0 and refclk1 of all
other transceiver blocks on the same side of the device
CMU0 PLL
Input Reference
CMU0 PLL
Clock
Figure
/1, /2, /4, /8
shows the CMU0 PLL.
1–89).
PFD
CMU0 PLL
chapter.
Charge Pump
+ Loop Filter
chapter.
Chapter 1: Transceiver Architecture in Stratix IV Devices
/M
V
CO
February 2011 Altera Corporation
Transceiver Block Architecture
/L
Reset Control
High-Speed
Transceiver
CMU0
Clock