DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 718
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 718 of 1154
- Download datasheet (32Mb)
2–46
Figure 2–26. Receiver Datapath Clocking in x4 Bonded Channel Configuration Without Deskew FIFO
Note to
(1) The red lines represent the FPGA fabric-Transceiver interface clock, the green lines represent the low-speed parallel clock, the dark red lines
Stratix IV Device Handbook Volume 2: Transceivers
represent the parallel recovered clock, and the blue lines represent the serial recovered clock.
Figure
rx_coreclk[0]
rx_coreclk[2]
rx_coreclk[1]
rx_coreclk[3]
Fabric
FPGA
FPGA Fabric_Transceiver
2–26:
Interface Clock
coreclkout
PCIe ×4 functional modes supports the ×4 bonded channel configuration without
deskew FIFO.
Figure 2–26
configurations without deskew FIFO.
x4 Bonded Channel Configuration Without Deskew FIFO
hard IP
hard IP
hard IP
hard IP
PCIe
PCIe
PCIe
PCIe
/2
Reference
Reference
Clock
Clock
Input
Input
Interface
Interface
Interface
Interface
PIPE
PIPE
PIPE
PIPE
shows the receiver datapath clocking in ×4 channel bonding
Compensation
Compensation
Compensation
Compensation
RX Phase
RX Phase
RX Phase
RX Phase
CMU1 PLL
CMU1 PLL
CMU0 PLL
FIFO
FIFO
FIFO
FIFO
Ordering
Ordering
Ordering
Ordering
Byte
Byte
Byte
Byte
Divider
CMU1
Clock
Divider
CMU0
Serializer
Serializer
Clock
Serializer
Serializer
Byte
/2
/2
Byte
/2
De-
Byte
De-
De-
Byte
/2
De-
CMU0 Channel
CMU1 Channel
Low-Speed Parallel Clock from CMU0 Clock Divider
Low-Speed Parallel Clock from CMU0 Clock Divider
Low-Speed Parallel Clock from CMU0 Clock Divider
Low-Speed Parallel Clock from CMU0 Clock Divider
Decoder
Decoder
Decoder
8B/10B
Decoder
8B/10B
8B/10B
8B/10B
Match
Match
Match
FIFO
FIFO
Rate
Rate
FIFO
Match
Rate
FIFO
Rate
Low-Speed Parallel Clock
Ch2 Parallel Recovered Clock
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Ch3 Parallel Recovered Clock
Ch0 Parallel Recovered Clock
Receiver Channel PCS
Chapter 2: Transceiver Clocking in Stratix IV Devices
Ch1 Parallel Recovered Clock
Aligner
Aligner
Aligner
Word
Aligner
Word
Word
Word
Channel 3
Channel 0
Channel 2
Channel 1
Transceiver Channel Datapath Clocking
Receiver Channel PMA
Receiver Channel PMA
Serializer
Receiver Channel PMA
Serializer
Serializer
Receiver Channel PMA
Serializer
De-
De-
De-
February 2011 Altera Corporation
De-
CDR
CDR
Serial Recovered Clock
CDR
Serial Recovered Clock
Serial Recovered Clock
Serial Recovered Clock
CDR
Input Reference Clock
Input Reference Clock
(Note 1)
Input Reference Clock
Input Reference Clock
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