DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 747

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
Configuration Examples
February 2011 Altera Corporation
Figure 2–38. Twenty-Four Channels on the Right Side of the EP4S100G5F45 Device Configured in
Basic (PMA Direct) ×N Mode for Configuration Example 1
Note to
(1) The green line represents the PLL cascade clock line and the blue lines represent the 6G ATX PLL block.
Figure
2–38:
(Transmitter Data
Generation Logic)
(Transmitter Data
Generation Logic)
FPGA Fabric
FPGA Fabric
FPGA CLK Pin
Dedicated
meet interface timing)
(VCO Bypass Mode)
(Phase Shift 315º to
PLL_R1
PLL_R2
PLL Cascade
Clock Line
Reference
tx_clkout
Clock
Transceiver Block GXBR3
Transceiver Block GXBR2
Transceiver Block GXBR0
Transceiver Block GXBR1
ATX PLL R2 (10G)
ATX PLL R1 (6G)
ATX PLL R0 (6G)
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Stratix IV Device Handbook Volume 2: Transceivers
(Note 1)
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xN_Top
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