DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 679

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
Input Reference Clocking
set_instance_assignment -name INPUT_TERMINATION OFF -to <refclk_pin_name>
February 2011 Altera Corporation
f
1
1
refclk0 and refclk1 Pins
Each transceiver block has two dedicated refclk pins that you can use to drive the
CMU PLL, receiver CDR, or both, input reference clocks. Each of the two CMU PLLs
and four receiver CDRs within a transceiver block can derive its input reference clock
from either the refclk0 or refclk1 pin.
The refclk pins provide the cleanest input reference clock path to the
CMU/ATX PLLs when compared with other input reference clock sources. Altera
recommends using the refclk pins to drive the CMU PLL input reference clock for
improved transmitter output jitter performance.
Table 2–4
on the refclk pins.
For specifications regarding the input frequency supported by the refclk pins, refer
to the
Table 2–4. Electrical Specifications for the Input Reference Clock
If you select the HCSL I/O standard for the PCIe reference clock, add the following
assignment to your project quartus settings file (.qsf):
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PCI Express
Notes to
(1) In PCIe mode, you have the option of selecting the HCSL standard for the reference clock if compliance to the PCIe
(2) Termination values supported are the same as the Receiver pin differential on-chip termination resistors specified
(3) For an example termination scheme, refer to
GIGE
XAUI
Serial RapidIO
SONET/SDH
SDI
(OIF) CEI PHY Interface
Basic
protocol is required. You can select this I/O standard option only if you configured the transceiver in PCIe functional
mode. For more information, refer to
in the
DC and Switching Characteristics for Stratix IV Devices
Table
Protocol
DC and Switching Characteristics for Stratix IV Devices
lists the electrical specifications for the input reference clock signal driven
®
2–4:
(PCIe)
®
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■
■
■
■
■
■
■
■
■
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1.2-V PCML, 1.4 PCML
1.4-V PCML
1.5-V PCML
2.5-V PCML
Differential LVPECL
LVDS
1.2-V PCML, 1.4 PCML
1.4-V PCML
1.5-V PCML
2.5-V PCML
Differential LVPECL
LVDS
HCSL
Figure 2–5 on page 2–8.
(1)
I/O Standard
Figure 2–5 on page
chapter.
Stratix IV Device Handbook Volume 2: Transceivers
2–8.
Coupling
chapter.
AC
AC
DC
Termination
Off-chip
On-chip
On-chip
(2)
(2)
(3)
2–7