DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 761

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Sharing CMU PLLs
February 2011 Altera Corporation
Table 3–3. ALTGX MegaWizard Plug-In Manager Settings for Example 1
You can force the placement of the transceiver channels to a specific transceiver block
by assigning pins to tx_dataout and rx_datain. Otherwise, the Quartus II software
selects a transceiver bank.
Figure 3–1
combines the transceiver channel instances. Because the RX CDR is not shared
between channels, only the CMU PLL is shown.
Note to
(1) The Specify base data rate option is 4.25 Gbps for all four instances. Given that the CMU PLL bandwidth setting
and input reference clock are the same and that the pll_powerdown ports are driven from the same logic or pin,
the Quartus II software shares a single CMU PLL that runs at 4.25 Gbps.
Table
Instance
inst3
and
3–3:
Figure 3–2
What is the effective data rate?
Specify base data rate
show the scenario before and after the Quartus II software
General Screen Option
Stratix IV Device Handbook Volume 2: Transceivers
Setting (Gbps)
4.25
4.25
(1)
3–7