DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 739

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation
Limitations of the Quartus II Software-Selected Receiver Phase Compensation FIFO Read
Clock
In non-bonded channel configurations without rate matcher, the Quartus II software
cannot determine if the incoming serial data in all channels has a 0 PPM frequency
difference. The Quartus II software uses the recovered clock rx_clkout signal from
each channel to clock the read port of its receiver phase compensation FIFO. This
results in one global, regional, or global and regional clock resource being used per
channel for the rx_clkout signal.
Figure 2–36
across four transceiver blocks. The incoming serial data to all 16 channels have a
0 PPM frequency difference with respect to each other. The Quartus II software uses
rx_clkout from each channel to clock the read port of its receiver phase compensation
FIFO. This results in 16 global, regional, or global and regional clock resources being
used, one for each channel.
Example 7: Sixteen Channels Across Four Transceiver Blocks
shows 16 non-bonded receiver channels without rate matcher, located
Stratix IV Device Handbook Volume 2: Transceivers
2–67