DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 662

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–218
Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 7 of 7)
Table 1–75. Stratix IV GX and GT ALTGX Megafunction Ports: CMU (Part 1 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
rx_locktorefclk
rx_signaldetect
rx_seriallpbken
pll_inclk
pll_locked
Port Name
Port Name
Table 1–75
Output
Output
Input/
Input
Output
Output
Input/
Input
Input
lists the ALTGX megafunction CMU ports.
Clock Domain
Asynchronous
Clock signal
Asynchronous
Asynchronous
Asynchronous
signal
Clock Domain
signal
signal
signal
Input reference clock for the CMU phase-locked
loop.
CMU PLL lock indicator.
■
■
A high level—the CMU PLL is locked to the
input reference clock.
A low level—the CMU PLL is not locked to the
input reference clock.
Receiver CDR lock-to-reference mode control
signal.
The rx_locktorefclk signal, along with the
rx_locktodata signal, controls whether the
receiver CDR is in automatic (0/0),
lock-to-reference (0/1), or lock-to-data (1/x)
mode.
Signal threshold detect indicator.
■
■
■
■
Serial loopback control port.
■
■
Available in Basic functional mode when the
8B/10B Encoder/Decoder is selected.
Available in PCIe mode.
A high level—that the signal present at the
receiver input buffer is above the
programmed signal detection threshold
value.
If the electrical idle inference block is
disabled in PCIe mode, the
rx_signaldetect signal is inverted and
driven on the pipeelecidle port.
0–normal datapath, no serial loopback
1–serial loopback
Chapter 1: Transceiver Architecture in Stratix IV Devices
Description
Description
February 2011 Altera Corporation
Transceiver Port Lists
Transceiver
Transceiver
Scope
block
block
Channel
Channel
Channel
Scope