DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 58

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

3–2
Table 3–1. Summary of TriMatrix Memory Features (Part 2 of 2)
Table 3–2. TriMatrix Memory Capacity and Distribution in Stratix IV Devices (Part 1 of 2)
Stratix IV Device Handbook Volume 1
Byte enable
Packed mode
Address clock enable
Single-port memory
Simple dual-port memory
True dual-port memory
Embedded shift register
ROM
FIFO buffer
Simple dual-port mixed
width support
True dual-port mixed width
support
Memory Initialization File
(.mif)
Mixed clock mode
Power-up condition
Register clears
Write/Read operation
triggering
Same-port read-during-write Outputs set to don’t care
Mixed-port read-during-write
ECC Support
EP4SE230
EP4SE360
EP4SE530
EP4SE820
EP4SGX70
EP4SGX110
Device
Feature
Table 3–2
Stratix IV family member.
MLABs
10,624
16,261
4,560
7,072
1,452
2,112
Outputs cleared if
registered, otherwise reads
memory contents
Output registers
Write: Falling clock edges
Read: Rising clock edges
Outputs set to old data or
don’t care
Soft IP support using the
Quartus II software
lists the capacity and distribution of the TriMatrix memory blocks in each
M9K Blocks
1,235
1,248
1,280
1,610
462
660
MLABs
v
—
v
v
v
—
v
v
v
—
—
v
v
M144K
Blocks
22
48
64
60
16
16
Outputs cleared
Output registers
Write and Read: Rising clock
edges
Outputs set to old data or
new data
Outputs set to old data or
don’t care
Soft IP support using the
Quartus II software
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
(Dedicated Memory Blocks Only)
Total Dedicated RAM Bits
M9K Blocks
v
v
v
v
v
v
v
v
v
v
v
v
v
14,283
18,144
20,736
23,130
6,462
8,244
(Kb)
Outputs cleared
Output registers
Write and Read: Rising clock
edges
Outputs set to old data or
new data
Outputs set to old data or
don’t care
Built-in support in ×64-wide
SDP mode or soft IP support
using the Quartus II software
February 2011 Altera Corporation
M144K Blocks
(Including MLABs)
Total RAM Bits
v
v
v
v
v
v
v
v
v
v
v
v
v
17,133
22,564
27,376
33,294
7,370
9,564
(Kb)
Overview