DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 667

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Port Lists
Table 1–77. Stratix IV GX and GT ALTGX Megafunction Ports: PCIe Interface (Part 4 of 4)
Table 1–78. Stratix IV GX and GT ALTGX Megafunction Ports: Reset and Power Down (Part 1 of 2)
February 2011 Altera Corporation
rx_pipedatavalid
pipeelecidle
gxb_powerdown
rx_digitalreset
Port Name
Port Name
Table 1–78
Output
Input/
Input
Input
Output
Output
Output
Input/
lists the ALTGX megafunction reset and power down ports.
refer the device
Characteristics
Clock Domain
Asynchronous
Asynchronous
requirements,
pulse width is
For minimum
clock cycles.
Clock Domain
Asynchronous
pulse width
two parallel
Switching
Minimum
chapter.
DC and
signal.
signal.
signal
N/A
Transceiver block power down.
■
■
Receiver PCS reset.
■
Valid data and control on the rx_dataout and
rx_ctrldetect ports indicator.
■
Electrical idle detected or inferred at the receiver
indicator.
■
■
■
When asserted high—all digital and analog
circuitry within the PCS, PMA, CMU channels, and
the CCU of the transceiver block, is powered down.
Asserting the gxb_powerdown signal does not
power down the REFCLK buffers.
When asserted high—the receiver PCS blocks are
reset. Refer to
Functionally equivalent to the rxvalid signal
defined in the PCIe specification revision 2.0.
Functionally equivalent to the rxelecidle
signal defined in the PCIe specification revision
2.0.
If the electrical idle inference block is enabled—
it drives this signal high when it infers an
electrical idle condition, as described in
“Electrical Idle Inference” on page
Otherwise, it drives this signal low.
If the electrical idle inference block is disabled—
the rx_signaldetect signal from the signal
detect circuitry in the receiver buffer is inverted
and driven on this port.
Reset Control and Power Down.
Stratix IV Device Handbook Volume 2: Transceivers
Description
Description
1–138.
Transceiver
1–223
Channel
Channel
Scope
Channel
Scope
block