DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 1040
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 1040 of 1154
- Download datasheet (32Mb)
2–22
Figure 2–5. FC4G Instance Settings (PLL/Ports Screen)
Stratix IV Device Handbook Volume 3
f
■
For more information about receiver CDR and lock modes, refer to the “Receiver
Channel Datapath” section of
PLL/Ports screen—Check the Train Receiver CDR from PLL inclk option, as
shown in
used for the CMU PLL is provided as a training clock to the receiver CDR.
■
■
■
Check the pll_powerdown signal. This signal allows you to power down the
CMU PLL. Use this signal as part of your reset sequence.
Check the pll_locked signal. This signal indicates whether the CMU PLL is
locked to the input reference clock. The user logic waits until the pll_locked
signal goes high before transmitting data.
Check the rx_freqlocked signal. This signal indicates whether the receiver
CDR is locked to data. When the receiver CDR is configured in automatic lock
mode, assert the rx_digitalreset signal if the rx_freqlocked signal goes low
to keep the receiver PCS under reset. Altera recommends specific transceiver
reset sequences to ensure proper device operation.
Figure
2–5. When you select this option, the same input reference clock
Transceiver Architecture in Stratix IV Devices
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Example 1: Fibre Channel Protocol Application
February 2011 Altera Corporation
chapter.
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