DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 649

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Calibration Blocks
Figure 1–172. Input Signals to the Calibration Blocks
February 2011 Altera Corporation
Calibration
Input Signals to the Calibration Block
The calibration block internally generates a constant internal reference voltage,
independent of process, voltage, or temperature variations. It uses the internal
reference voltage and external reference resistor (you must connect the resistor to the
RREF pin) to generate constant reference currents. These reference currents are used by
the analog block calibration circuit to calibrate the transceiver blocks.
The OCT calibration circuit calibrates the OCT resistors present in the transceiver
channels. You can enable the OCT resistors in the transceiver channels through the
ALTGX MegaWizard Plug-In Manager.
You must connect a separate 2 kΩ (tolerance max ± 1%) external resistor on each RREF
pin in the Stratix IV GX and GT device to ground. To ensure proper operation of the
calibration block, the RREF resistor connection in the board must be free from external
noise.
The ALTGX MegaWizard Plug-In Manager provides the cal_blk_clk and
cal_blk_powerdown ports to control the calibration block:
■
■
Figure 1–172
cal_blk_powerdown
cal_blk_clk—you must use the cal_blk_clk port to provide input clock to the
calibration clock. The frequency of cal_blk_clk must be within 10 MHz to
125 MHz (this range is preliminary. Final values will be available after
characterization). You can use dedicated clock routes such as the global or regional
clock. If you do not have suitable input reference clock or dedicated clock routing
resources available, use divide-down logic from the FPGA fabric to generate a
slow clock and use local clocking routing. Drive the cal_blk_clk port of all
ALTGX instances that are associated with the same calibration block from the
same input pin or logic.
cal_blk_powerdown—you can perform calibration multiple times by using the
cal_blk_powerdown port available through the ALTGX MegaWizard Plug-In
Manager. Assert this signal for approximately 500 ns. Following de-assertion of
cal_blk_powerdown, the calibration block restarts the calibration process. Drive the
cal_blk_powerdown port of all ALTGX instances that are associated with the same
calibration block from the same input pin or logic.
OCT Calibration
Control
cal_blk_clk
RREF pin
shows the required inputs to the calibration block.
OCT Calibration
Circuit
Calibration Block
Reference
Generator
Internal
Voltage
Reference
Calibration Circuit
Signal
Analog Block
Stratix IV Device Handbook Volume 2: Transceivers
Calibration Control
Analog Block
1–205