DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 680

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–8
Figure 2–5. Termination Scheme for a Reference Clock Signal When Configured as HCSL
Notes to
(1) No biasing is required if the reference clock signals are generated from a clock source that conforms to the PCIe specification.
(2) Select resistor values as recommended by the PCIe clock source vendor.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
2–5:
f
1
Figure 2–5
configured as HCSL.
Inter-Transceiver Block (ITB) Clock Lines
The refclk0 and refclk1 pins of other transceiver blocks using the ITB clock lines
provide an input reference clock path from the refclk pins of one transceiver block to
the CMU PLLs and receiver CDRs of the other transceiver blocks. In designs that have
channels located in different transceiver blocks, the ITB clock lines eliminate the need
to connect the on-board reference clock crystal oscillator to the refclk pin of each
transceiver block. The ITB clock lines also drive the clock signal on the refclk pins to
the clock logic in the FPGA fabric.
The ITB clock lines also provide an input reference clock path from the refclk pins of
any transceiver block to the ATX PLLs located on the same side of the device.
Each refclk pin drives one ITB clock line for a total of up to eight ITB clock lines on
each of the right and left sides of the device, as shown in
The ITB clock lines provide input reference clock paths from the refclk pins of one
transceiver block to the CMU PLLs and receiver CDRs of other transceiver blocks
located on the same side of the device.
Dedicated CLK Input Pins on the FPGA Global Clock Network
Stratix IV devices provide up to eight differential clock input pins located in
non-transceiver I/O banks that you can use to provide up to eight input reference
clocks to the transceiver blocks. The Quartus
global clock network to route the input reference clock signal from the CLK pins to the
transceiver blocks.
For more information, refer to the “Dedicated Clock Input Pins” section in the
Networks and PLLs in Stratix IV Devices
One global clock resource is available for each CMU PLL, 6G ATX PLL, and receiver
CDR. This allows each CMU PLL, 6G ATX PLL, and receiver CDR to derive its input
reference clock from a separate FPGA CLK input pin.
PCI Express
(HCSL)
Source
refclk
shows an example termination scheme for a reference clock signal when
Rp
Rs
Rs
=
(2)
(2)
50 Ω
Rp
chapter.
=
50 Ω
®
Chapter 2: Transceiver Clocking in Stratix IV Devices
II software automatically chooses the
refclk
refclk
Stratix IV
Figure 2–3 on page
+
-
(Note 1)
February 2011 Altera Corporation
Input Reference Clocking
2–5.
Clock