DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 779

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transceiver Channels in Basic (PMA Direct) Configurations
Table 3–8. PCIe Hard IP Block Restrictions When Combining Transceiver Channels with Different Functional and/or
Protocol Modes (Part 2 of 2)
Combining Transceiver Channels in Basic (PMA Direct) Configurations
February 2011 Altera Corporation
Notes to
(1) Avail. indicates that the channels can be used in other configurations.
(2) An em-dash (—) indicates that the channels are NOT available for use.
(3) The CMU PLL is used for the transmitter side of the channels in this table.
(4) Transceiver block 0—the master transceiver block that provides high-speed serial and low-speed parallel clocks in a PCIe ×4 or ×8
(5) Transceiver block 1—the adjacent transceiver block that shares the same PCIe hard IP block with transceiver block 0.
(6) The physical channel 0 in the transceiver block. For more information about physical-to-logical channel mapping in PCIe functional mode, refer
(7) When you the use PCIe hard IP Block, you cannot configure the CMU channels within the transceiver block as transceiver channels.
Compiler MegaWizard Plug-In Manager)
Width
Link
Options Enabled in the PCI Express
×4
×8
PCIe Configuration (PCIe hard IP
configuration.
to the “×8 Channel Configuration” section in the
Table
(Data Interface
3–8:
f
f
f
128-bit
Width)
Lane
—
(3)
For more information about the PCI Express Compiler MegaCore functions and hard IP
implementation, refer to the
If you configure a transceiver channel in PCIe configuration and if an ATX PLL is
used to provide clocks for the transmitter side of the channel, you can use the
remaining transmitter channels within the same transceiver block only in Basic (PMA
Direct) ×1 or ×N mode.
In this configuration, the transmitter and receiver PCS blocks of a transceiver channel
are bypassed and the transceiver channel can run at a maximum of 6.5 Gbps.
For the data rate restrictions in Basic (PMA Direct) mode, refer to the “Transceiver
Performance Specifications” section in the
Stratix IV Devices
Using the Quartus II software, you can configure the two CMU channels and regular
transceiver channels in Basic (PMA Direct) mode. The following sections describes the
different scenarios for combining Basic (PMA Direct) mode with other transceiver
configurations.
For information about the FPGA fabric-transceiver interface, refer to the
“Non-Bonded Basic (PMA Direct) Mode Channel Configurations” section in the
Transceiver Clocking in Stratix IV Devices
(Note
Channel
Virtual
(VC)
—
1
2
1), (2),
chapter.
Ch0
Transceiver Clocking in Stratix IV Devices
(7)
(6)
Transceiver Block 0
PCI Express Compiler User Guide.
Ch1
PCIe ×4
PCIe ×4
Ch2
chapter.
(4)
DC and Switching Characteristics for
Ch3
PCIe ×8
chapter.
Stratix IV Device Handbook Volume 2: Transceivers
Avail.
Ch4
—
Transceiver Block 1
Avail.
Ch5
—
Avail.
Avail.
Ch6
(5)
Avail.
Avail.
Ch7
3–25