DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 133

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
Figure 5–15. clkena Signals
Note to
(1) You can use the clkena signals to enable or disable the GCLK and RCLK networks or the PLL_<#>_CLKOUT pins.
February 2011 Altera Corporation
output of AND gate
with R2 not bypassed
Figure
output of AND gate
with R2 bypassed
Clock Enable Signals
output of clock
select mux
5–15:
clkena
Figure 5–14
is implemented in Stratix IV devices.
Figure 5–14. clkena Implementation
Notes to
(1) The R1 and R2 bypass paths are not available for the PLL external clock outputs.
(2) The select line is statically controlled by a bit setting in the configuration file (.sof or .pof).
In Stratix IV devices, the clkena signals are supported at the clock network level
instead of at the PLL output counter level. This allows you to gate off the clock even
when you are not using a PLL. You can also use the clkena signals to control the
dedicated external clocks from the PLLs.
a clock output enable. clkena is synchronous to the falling edge of the clock output.
Stratix IV devices also have an additional metastability register that aids in
asynchronous enable and disable of the GCLK and RCLK networks. You can
optionally bypass this register in the Quartus II software.
(Note 1)
Figure
output of clock
select mux
shows how the clock enable and disable circuit of the clock control block
5–14:
clkena
D
(1)
R1
Q
D
R2
(1)
Q
Figure 5–15
(2)
shows a waveform example for
Stratix IV Device Handbook Volume 1
GCLK/
RCLK/
PLL_<#>_CLKOUT (1)
5–17