DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 631
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 631 of 1154
- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–153. Rate Match FIFO Deletion with One Skip Pattern Inserted
February 2011 Altera Corporation
dataout
datain
f
1
K28.5
K28.5
First Skip Cluster
Figure 1–153
skip pattern is required to be inserted. In this example, the first skip cluster has a
/K28.5/ control pattern followed by three /K29.7/ skip patterns. The second skip
cluster has a /K28.5/ control pattern followed by two /K29.7/ skip patterns. The rate
match FIFO inserts only one /K29.7/ skip pattern into the first skip cluster. One
/K29.7/ skip pattern is inserted into the second cluster.
Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the FPGA fabric to
indicate rate match FIFO full and empty conditions. For more information about the
behavior of these two signals, refer to
on page
Basic (PMA Direct) Functional Mode
In Basic (PMA Direct) functional mode, the Stratix IV GX and GT transceiver datapath
contains only PMA blocks. Parallel data is transferred directly between the FPGA
fabric and the serializer/deserializer inside the transmitter/receiver PMA. Because all
PCS blocks are bypassed in Basic (PMA Direct) mode, you must implement the
required PCS logic in the FPGA fabric.
You can configure four regular transceiver channels inside each transceiver block in
Basic (PMA Direct) functional mode. You can configure two CMU channels inside
each transceiver block only in Basic (PMA Direct) functional mode, as they do not
support PCS circuitry.
In PMA Direct mode, you must create your own logic to support PCS functionality.
There are specific reset sequences to be followed in this mode.
Use dynamic reconfiguration to dynamically reconfigure the various PMA controls to
tailor the transceivers in PMA direct drive mode for a particular application.
For more information, refer to the
chapter. For more information about the reset sequence to follow in PMA-Direct
mode, refer to the
The term ‘PMA-Direct’ is used to describe various configurations in this mode.
In Basic (PMA Direct) mode, all the PCS blocks are bypassed; therefore, any PCS-type
features (for example, phase compensation FIFOs, byte serializer, 8B/10B
encoder/decoder, word aligner, deskew FIFO, rate match FIFO, byte deserializer, and
byte ordering), must be implemented in the FPGA fabric. In Basic (PMA Direct) mode,
you must create your own logic to support PCS functionality.
K29.7
K29.7
1–84.
K29.7
K29.7
shows an example of rate match FIFO insertion in the case where one
Reset Control and Power Down in Stratix IV Devices
K29.7
K29.7
One Skip Pattern Inserted
K29.7
K28.5
Dynamic Reconfiguration in Stratix IV Devices
Second Skip Cluster
“Rate Match FIFO in Basic Single-Width Mode”
K29.7
K28.5
K29.7
K29.7
Stratix IV Device Handbook Volume 2: Transceivers
Dx.y
K29.7
K29.7
chapter.
Dx.y
1–187
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