DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 286
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 286 of 1154
- Download datasheet (32Mb)
8–8
LVDS SERDES
Figure 8–4. LVDS SERDES
Notes to
(1) This diagram shows a shared PLL between the transmitter and receiver. If the transmitter and receiver are not sharing the same PLL, the two left
(2) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(3) The tx_in and rx_out ports have a maximum data width of 10 bits.
Stratix IV Device Handbook Volume 1
tx_coreclock
rx_divfwdclk
rx_outclock
and right PLLs are required.
FPGA
Fabric
rx_out
tx_in
Figure
8–4:
10
10
Figure 8–4
circuitry in the left and right banks. This diagram shows the interface signals of the
transmitter and receiver data path. For more information, refer to
Transmitter” on page 8–11
3
(LOAD_EN, diffioclk)
IOE Supports SDR, DDR, or
2
(Note
(LVDS_LOAD_EN, diffioclk,
DIN DOUT
Non-Registered Datapath
Deserializer
DOUT
Serializer
1), (2),
tx_coreclock)
DIN
shows a transmitter and receiver block diagram for the LVDS SERDES
IOE
2
Left/Right PLL
2
(3)
3
DOUT
Clock MUX
(LVDS_LOAD_EN,
Bit Slip
LVDS_diffioclk,
IOE
rx_outclock
diffioclk
DIN
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
and
rx_inclock/tx_inclock
“Differential Receiver” on page
LVDS Transmitter
LVDS Receiver
DOUT
Synchronizer
IOE Supports SDR, DDR, or
Non-Registered Datapath
DIN
8 Serial LVDS
Clock Phases
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
Retimed
DPA Clock
Data
DPA Circuitry
February 2011 Altera Corporation
DIN
8–17.
“Differential
+
-
LVDS Clock Domain
DPA Clock Domain
+
-
LVDS SERDES
rx_in
tx_out
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