DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 332

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

9–4
Power-On Reset Circuitry
Figure 9–2. Simplified POR Diagram for Stratix IV Devices
Stratix IV Device Handbook Volume 1
V
V
V
V
V
CCPGM
CC
CCPD
CCPT
CCAUX
1
1
When power is applied to a Stratix IV device, a POR event occurs if the power supply
reaches the recommended operating range within the maximum power supply ramp
time (t
remain tri-stated, during which device configuration could fail. The maximum t
for Stratix IV devices is 100 ms; the minimum t
high, the maximum T
Stratix IV devices provide a dedicated input pin (PORSEL) to select a POR delay time
during power up. When the PORSEL pin is connected to GND, the POR delay time is
100 to 300 ms. When the PORSEL pin is set to high, the POR delay time is 4 to 12 ms.
The POR block consists of a regulator POR, satellite POR, and main POR to check the
power supply levels for proper device configuration.
The satellite POR monitors the following:
■
■
■
Altera requires powering up V
The main POR waits for satellite POR and the regulator POR to release the POR
signal. Until the release of the POR signal, the device configuration cannot start.
The internal configuration memory supply that is used during device configuration is
checked by the regulator POR block and is gated in the main POR block for the final
POR trip.
All configuration-related dedicated and dual function I/O pins must be powered by
V
CCPGM
Regulator POR
V
programming
V
technology
V
Satellite POR
CCPD
CCAUX
CC
R AMP
.
and V
Figure 9–2
and V
). If t
power supply which is the auxiliary supply for the programmable power
CCPT
RAMP
CCPGM
power supplies that are used in the device core
shows a simplified diagram of the POR block.
is not met, the device I/O pins and programming registers
RAMP
power supplies that are used in the I/O buffers and for device
for Stratix IV devices is 4 ms.
PORSEL
CC
before V
Chapter 9: Hot Socketing and Power-On Reset in Stratix IV Devices
CCAUX
RAMP
.
POR Pulse
is 50 µs. When the PORSEL pin is
Main POR
Setting
February 2011 Altera Corporation
Power-On Reset Circuitry
POR
RAMP