DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 625

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–147. (OIF) CEI PHY Interface Mode for Stratix IV GX and GT Devices
February 2011 Altera Corporation
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
PMA-PCS Interface
Interface Frequency
Fabric-Transceiver
Low-Latency PCS
Fabric-Transceiver
(OIF) CEI PHY Interface Mode
Stratix IV GX and GT transceivers support a data rate between 4.976 Gbps and
6.375 Gbps in (OIF) CEI PHY interface mode.
Figure 1–147
Stratix IV GX and GT devices.
Encoder/Decoder
Rate Match FIFO
Functional Modes
Data Rate (Gbps)
Channel Bonding
TX PCS Latency
Interface Frequency
Functional Mode
(Pattern Length)
RX PCS Latency
Byte Ordering
Interface Width
Word Aligner
Byte SerDes
8B/10B
Width
FPGA
FPGA
(MHz)
8-bit
shows (OIF) CEI PHY interface mode configurations supported in
Single
Width
10-bit
Basic
16-bit
Double
Width
Stratix IV GX and GT Configurations
20-bit
10-bit
PIPE
XAUI
10-bit
GIGE
10-bit
Protocol
SRIO
10-bit
SONET
/SDH
8-bit
Stratix IV Device Handbook Volume 2: Transceivers
x1, x4 (Transmitter
PMA-Only Bonding)
(OIF) CEI PHY
Interface Mode
199.21875
3.125-6.375
97.65625-
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
4 -5.5
16-bit
32-Bit
6.5 -
(OIF)
CEI
8.5
10-bit
SDI
10-Bit
Deterministic
Latency
20-Bit
1–181