DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 1030

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Verification
Verification
Functional Simulation
February 2011 Altera Corporation
f
f
1
The SignalTap
on-chip logic analyzer. SignalTap provides options to create multiple sets of signals
that can be sampled using different trigger clocks. You can add the signals to the
SignalTap Logic Analyzer and save the file as an STP file (.stp). When you include this
.stp along with the design files and compile the design, the Quartus II software creates
an .sof that allows you to verify the functionality of the signals that you added in the
SignalTap Logic Analyzer file.
You can run the .stp that connects to the device through the JTAG port and displays
the signal transitions using the Quartus II software. Because the JTAG port is required
to run SignalTap, consider designing the board with the JTAG interface for debugging
your system.
For more information about using SignalTap, refer to the
SignalTap II Embedded Logic Analyzer
Software Handbook.
To verify the functionality of the PCS and PMA blocks, the Stratix IV GX transceiver
provides diagnostic loopback features between the transmitter and the receiver
channels.
For more information, refer to the “Loopback Modes” section in the
Architecture in Stratix IV Devices
Use the ALTGX MegaWizard Plug-In Manager-generated wrapper file to simulate the
instantiated transceiver configuration in third-party simulation software such as
ModelSim. For simulation, specific Altera
in
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These simulation files are available under the following folder in the Quartus II
installation directory: <Quartus II installation folder>/eda/sim_lib
The stratixiv_hssi_component library file is only applicable if the transceiver instance
is created using VHDL.
Table
220pack
220model
altera_mf_components
altera_mf
sgate_pack
sgate
stratixiv_hssi_component
stratixiv_hssi_atoms
2–1). The following library files are available in VHDL and Verilog versions:
®
Logic Analyzer allows you to verify design functionality using the
chapter.
section in volume 3 of the Quartus II Development
®
simulation library files are required (listed
Design Debugging Using the
Stratix IV Device Handbook Volume 3
Transceiver
2–12