DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 725

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation
1
Example 3 assumes channels 0 and 1, driven by CMU0_PLL in a transceiver block, are
identical. Also, channels 2 and 3, driven by CMU1_PLL in the same transceiver block,
are identical. In this case, the Quartus II software automatically drives the write port
of the transmitter phase compensation FIFO in channels 0 and 1 with the
tx_clkout[0] signal. It also drives the write port of the transmitter phase
compensation FIFO in channels 2 and 3 with the tx_clkout[2] signal. Use the
tx_clkout[0] signal to clock the transmitter data and control logic for channels 0
and 1 in the FPGA fabric. Use the tx_clkout[2] signal to clock the transmitter data
and control logic for channels 2 and 3 in the FPGA fabric.
This configuration uses two FPGA global and/or regional clock resources, one for the
tx_clkout[0] signal and the other for the tx_clkout[2] signal.
Example 3: Two Groups of Two Identical Channels in a Transceiver Block
Stratix IV Device Handbook Volume 2: Transceivers
2–53