DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 753

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
Configuration Examples
qmegawiz -silent -wiz_override="c1_test_source=1,c1_mode=BYPASS,clk1_counter=C1" pll0.v
February 2011 Altera Corporation
1
3. Under the Output Clocks tab turn off Use this clock for clk c0.
4. Turn on Use this clock for clk c1
Figure 2–43. Use This Clock Option Used for Configuration Example 4
5. Click Finish for the MegaWizard Plug-In Manager to generate the verilog .v file
6. Next, from the command line, go to the directory where you have the ALTPLL
VCO bypass mode is not supported in the .mif file. Therefore, you can not manually
modify the .mif file to set the PLL in VCO bypass mode.
7. Finally, connect clk c1output of the left and right, left, or right PLL to the input
1
for the ALTPLL instantiation.
instance files (.v or .vhdl) and type the following command:
This command places your ALTPLL instance in VCO bypass mode. Revisit the .v
or .vhdl file associated with the ALTPLL instance. Examine the file which is
automatically updated to incorporate the PLL in a VCO bypass mode.
reference clock port of the ATX PLL used to generate the transceiver clocks.
The VCO bypass option is only enabled for clock output c1.
(Figure
2–43).
Stratix IV Device Handbook Volume 2: Transceivers
2–81