DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 819
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
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- Download datasheet (32Mb)
Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transceiver Reset Sequences
February 2011 Altera Corporation
As shown in
reset steps:
1. After power up, assert pll_powerdown for a minimum period of t
2. Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset signals
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high,
4. For the receiver operation, after de-assertion of the busy signal, wait for a
5. Wait for the rx_freqlocked signal from each channel to go high. The
6. In a bonded channel group, when the rx_freqlocked signals of all the channels
time between markers 1 and 2).
asserted during this time period. After you de-assert the pll_powerdown signal, the
transmitter PLL starts locking to the transmitter input reference clock.
de-assert the tx_digitalreset signal. At this point, the transmitter is ready for
data traffic.
minimum of two parallel clock cycles to de-assert the rx_analogreset signal.
After rx_analogreset is de-asserted, the receiver CDR of each channel starts
locking to the receiver input reference clock.
rx_freqlocked signal of each channel may go high at different times (indicated by
the slashed pattern at marker 7).
have gone high, from that point onwards, wait for at least t
receiver parallel clock to stabilize, then de-assert the rx_digitalreset signal
(marker 8). At this point, all the receivers are ready for data traffic. Note that
rx_digitalreset must not be released if there is no data present at the receiver
pins to avoid overflow/underflow of the phase compensation FIFOs.
Figure
4–6, for the receiver CDR in automatic lock mode, follow these
Stratix IV Device Handbook Volume 2: Transceivers
LTD_Auto
pll_powerdown
for the
(the
4–13
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