DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 977

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Table 1–3. MegaWizard Plug-In Manager Options (Ports/Calibration Screen) (Part 3 of 3)
February 2011 Altera Corporation
Create an active high
cal_blk_powerdown to power down
the calibration block.
What is the Analog Power (V
ALTGX Setting
CCA_L/R
)?
Asserting this signal high powers
down the calibration block. A
high-to-low transition on this signal
restarts calibration.
The options available for selection
are based on what you specify in the
Specify base data rate option:
■
■
■
■
It is up to you to connect the correct
voltage supply to the V
the board.
3.3 V—Available up to 11.3 Gbps
for Stratix IV GT devices only.
3.0 V—Available up to 8.5 Gbps.
2.5 V—Available up to 4.25 Gbps.
AUTO—The ALTGX MegaWizard
Plug-In Manager automatically
sets V
data rates less than 4.25 Gbps.
or
V
rates greater than 4.25 Gbps.
CCA_L/R
CCA_L/R
to 3.0 V for the VCO data
Description
to 2.5 V for the VCO
CCA_L/R
pins on
“Input Signals to the Calibration Block”
section in the
Stratix IV Devices
“General Requirements to Combine
Channels” section in the
Multiple Protocols and Data Rates in
Stratix IV Devices
Stratix IV Device Handbook Volume 3
Transceiver Architecture in
Reference
chapter.
chapter.
Configuring
1–19