DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 526

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

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Figure 1–65. Rate Match Insertion in XAUI Mode
Stratix IV Device Handbook Volume 2: Transceivers
rx_rmfifodatainserted
dataout[3]
dataout[2]
dataout[1]
dataout[0]
datain[3]
datain[2]
datain[1]
datain[0]
1
Figure 1–65
columns are required to be inserted.
Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the FPGA fabric to
indicate rate match FIFO full and empty conditions.
In XAUI mode, the rate match FIFO does not automatically insert or delete code
groups to overcome FIFO empty and full conditions, respectively. It asserts the
rx_rmfifofull and rx_rmfifoempty flags for at least three recovered clock cycles to
indicate rate match FIFO full and empty conditions, respectively.
In the case of rate match FIFO full and empty conditions, you must assert the
rx_digitalreset signal to reset the receiver PCS blocks.
In GIGE mode, the rate match FIFO is capable of compensating for up to ±100 PPM
(200 PPM total) difference between the upstream transmitter and the local receiver
reference clock. The GIGE protocol requires the transmitter to send idle ordered sets
/I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps, adhering
to rules listed in the IEEE 802.3 specification.
The rate match operation begins after the synchronization state machine in the word
aligner indicates synchronization is acquired by driving the rx_syncstatus signal
high. The rate match FIFO is capable of deleting or inserting the /I2/
(/K28.5/D16.2/) ordered set to prevent the rate match FIFO from overflowing or
under running during normal packet transmission. The rate match FIFO is also
capable of deleting or inserting the first two bytes of the /C2/ ordered set
(/K28.5/D2.2/Dx.y/Dx.y/) to prevent the rate match FIFO from overflowing or
under running during the auto negotiation phase.
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Rate Match FIFO in GIGE Mode
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shows an example of rate match insertion in the case where two ||R||
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Chapter 1: Transceiver Architecture in Stratix IV Devices
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February 2011 Altera Corporation
Transceiver Block Architecture
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